1. Technical Field
The present invention relates generally to equalization techniques for high-speed data communications and more specifically to implementations of decision feedback equalizer (DFE) circuits with improved performance.
2. Description of the Related Art
With advances in digital computing capabilities fueled by scaling of semiconductor technologies, demands for high-bandwidth transmission of data in systems such as servers and data communication routers continue to increase. However, the limited bandwidth of electrical channels makes it difficult to increase data rates beyond a few gigabits per second. Channel bandwidth degradation is the result of many physical effects, including skin effect, dielectric loss, and reflections due to impedance discontinuities. Consequently, high data rate pulses transmitted through these channels will broaden to greater than a unit interval (UI), thus creating intersymbol interference (ISI) with preceding bits (precursors) and succeeding bits (postcursors).
One method of compensating signal distortion due to ISI is to add equalization to the transmitting or receiving circuitry. In particular, a nonlinear decision feedback equalizer (DFE) is preferred over linear equalization techniques for equalizing high-loss channels. Unlike linear equalizers, a DFE reduces signal distortion without amplifying noise or crosstalk from adjacent channels, making it well-suited for equalizing channels where the loss exceeds, e.g., 20-30 dB.
In a DFE, previous bit decisions are fed back with weighted tap coefficients and added to the received input signal. The tap coefficients are adjusted, either manually or by means of an adaptive algorithm, to match the inverse of the channel characteristics. Consequently, ISI is removed from the received input signal such that a decision can be made on the received bit with a low bit error rate (BER). It is common for the addition function to be implemented using a current-mode logic (CML) analog summer. In such an implementation, current from multiple differential pairs is steered into a resistive load. The voltage at the output of the summer is proportional to a linear combination of the input signal plus the weighted feedback taps.
One drawback of this resistive approach is that as more feedback taps are added to compensate for multiple postcursors, the capacitive loading at the summation node increases hence degrading its settling time. While the load resistance can be decreased to improve settling time, this requires higher current levels and thus higher power consumption to achieve a desired differential output voltage.